The present invention relates to switching amplifiers and, more specifically, to improved techniques for reducing or minimizing DC offset voltages in switching amplifiers.
In virtually any amplification system, a standard design goal is the minimization of DC offset voltage. DC offset voltage is defined as a non-zero DC voltage observed at the amplifier output when zero DC voltage is applied to the input. In an audio amplifier, the DC offset voltage can appear suddenly at the output terminals (and thus at the speakers) at the instant the amplifier is energized or activated, producing an unpleasant thump or pop. This phenomenon is observed in both linear and switching (class-D) amplifiers.
Minimization of DC offset voltage can be achieved by the use of carefully matched circuit elements, by adaptive (i.e., self-adjusting) mechanisms, or both. Some amplification systems are designed with relays between their output stages and the speakers that are open at the time the amplifier is energized and close only after a very slow acting continuous time servo loop has had sufficient time to null the output offset. The use of relays is costly, however, and can impact reliability as well. The slow acting servo loop also requires a time constant that is large (it must be significantly greater than the period of the lowest audio frequency being amplified) and is therefore difficult to integrate onto a silicon chip. Digital implementation of this same form of slow, real-time servo loop requires a large number of bits (e.g., 16 or more) which is also prohibitive.
Another technique employs a sub-block of a switching amplifier processor IC that nulls the output offset using a modest DAC (e.g., one 10-bit DAC per channel) and digital control circuitry. Each DAC's output is summed into its respective channel input along with the incoming signal. Offset cancellation occurs before amplification begins and after a predetermined stabilization period that follows the call for amplification. This stabilization period allows for settling of local time constants, e.g., the charging of the amplifier's input DC blocking capacitor(s). A DC offset cancellation routine then runs between the end of the stabilization period and the onset of actual switching amplification.
During the DC offset cancellation routine, digital control circuitry searches out a DAC value that substantially cancels output-referred offset. After completion of the routine, each channel's DAC will apply a DC signal to its respective channel input that effectively cancels systematic offsets as observed at the amplifier outputs. Once the offset cancellation DAC input value for each channel is determined, it is latched and the amplifier is enabled for normal amplification. The DAC input value for each channel remains constant throughout the duration of amplification until the amplifier is either muted or turned off. The DC offset cancellation routine is executed anew each time the amplifier is energized regardless of the previous offset cancellation results in order to accommodate any thermal drift or other changes that may have affected the amplifier over time.
In the bridged type of amplifier a special concern arises from the non-zero common mode output voltage (Vcm) present during amplification. Most bridged type amplifiers use only one voltage supply for the output power stage (usually positive and referred to herein as Vdd). In fact, the choice of a bridged type output stage is often made specifically so that only a single power supply is needed while maintaining a peak to peak output voltage swing of 2×Vdd. Since the positive and negative amplifier output terminals (V+ and V−, respectively) can each swing only between ground (0V) and Vdd, and assuming they are truly complementary, the common mode voltage (Vcm) is Vdd/2. Any mismatch between the resistors in the differential feedback path will introduce an offset component that is proportional to Vcm. Thus, during the execution of the offset cancellation routine, it is necessary to bias the amplifier outputs such that V+=V−=Vdd/2 (or to mimic these same conditions by other means), just as is the case during normal amplification, in order for the DC offset cancellation block to properly accommodate any offset that might exist in the differential resistive feedback path from the power stage.
Achieving the mid-rail condition of V+=V−=Vdd/2 at conventional 2-state switching outputs is difficult, however. Any scheme that attempts to do this (for example, by placing the output stage(s) in a tri-stated condition and introducing a resistive divider network between Vdd and ground via transmission gates or even relays) adds components, reduces reliability, and may introduce a pop or click into the speakers when engaged or disengaged. A permanent resistor divider network could be used, but it would waste power and would also add unnecessary components to the system.
In one previous technique (described in pending U.S. patent application Ser. No. 10/127,357 for DC OFFSET SELF-CALIBRATION SYSTEM FOR A DIGITAL SWITCHING AMPLIFIER filed Apr. 19, 2002, the entire disclosure of which is incorporated herein by reference), a DC offset cancellation block includes a single 10-bit (9 weighted bits plus sign bit) successive approximation register (SAR) and a 10-bit DAC (or one 10-bit DAC per channel in a multi-channel system) with control/sequencing circuitry. The described technique is quite time-efficient (in practice each channel can take approximately 1.5 ms to calibrate), but it is logic-intensive and therefore silicon area intensive. For example, a 4-channel DC offset cancellation block implemented according to such a technique may contain the equivalent of 1900 gates (one gate being equivalent in size to a single logic inverter). It also does not down-scale well, i.e., if reduced to two channels, the gate count is still approximately 1650.
The successive approximation register (SAR) method mentioned above consumes a significant amount of circuit area with digital circuitry. This is particularly problematic if the IC process on which the circuitry is manufactured is optimized for analog design or even for high voltage circuitry and does not have deep submicron devices available to help in constructing compact digital circuitry.
It is therefore desirable to provide improved techniques for reducing or minimizing DC offset in switching amplifiers.